#ifndef H_GDU_FPGA_H
#define H_GDU_FPGA_H

#define msleep(ms) usleep( ms * 1000 )

#define PA_INDEX			0*32
#define PB_INDEX			1*32
#define PC_INDEX			2*32

#define PIN_EB_PWR			22+PB_INDEX  // PB22

#define PIN_CLK				26+PB_INDEX  // PB26
#define PIN_DIN				27+PB_INDEX  // PB27
#define PIN_PRG				29+PB_INDEX  // PB29
#define PIN_DONE			28+PB_INDEX  // PB28

#define PIN_LATCH_CNT		30+PB_INDEX  // PB30
#define PIN_CLR_CNT			31+PB_INDEX  // PB31

#define PIN_DAC_CS	  		8+PC_INDEX	  //PC12
#define PIN_DAC_CLK	  		0+PB_INDEX	  //PB0
#define PIN_DAC_DIN	  		1+PB_INDEX	  //PB1


#define	SetFPGAClk()		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_CLK )
#define	SetFPGAData()		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_DIN )
#define	SetFPGAProg()		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_PRG )
#define SetFPGADone()		ioctl( fd, IOCTL_GPIO_DIR_IN, PIN_DONE )

#define	SetFPGAmLatch()		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_LATCH_CNT );
#define	SetFPGAmClear()		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_CLR_CNT	 );
	
#define	SetFPGAProgHigh()	ioctl( fd, IOCTL_GPIO_OUT_SET, PIN_PRG );	
#define	SetFPGAProgLow()	ioctl( fd, IOCTL_GPIO_OUT_CLR, PIN_PRG );	

#define	SetFPGAClkHigh()	ioctl( fd, IOCTL_GPIO_OUT_SET, PIN_CLK );
#define	SetFPGAClkLow()		ioctl( fd, IOCTL_GPIO_OUT_CLR, PIN_CLK );

#define	SetFPGADataHigh()	ioctl( fd, IOCTL_GPIO_OUT_SET, PIN_DIN );
#define	SetFPGADataLow()	ioctl( fd, IOCTL_GPIO_OUT_CLR, PIN_DIN );

#define	SetFPGAmLatchHigh()	ioctl( fdFPGA, IOCTL_GPIO_OUT_SET, PIN_LATCH_CNT )
#define	SetFPGAmLatchLow()	ioctl( fdFPGA, IOCTL_GPIO_OUT_CLR, PIN_LATCH_CNT )

#define	SetFPGAmClearHigh()	ioctl( fd, IOCTL_GPIO_OUT_SET, PIN_CLR_CNT )
#define	SetFPGAmClearLow()	ioctl( fd, IOCTL_GPIO_OUT_CLR, PIN_CLR_CNT )

#define	GetFPGADone()		ioctl( fd, IOCTL_GPIO_LEVEL , PIN_DONE )



#define SetDacCsHigh(x)  	ioctl( x, IOCTL_GPIO_OUT_SET, PIN_DAC_CS )
#define SetDacCsLow(x)  	ioctl( x, IOCTL_GPIO_OUT_CLR, PIN_DAC_CS )

#define SetDacClkHigh(x)  	ioctl( x, IOCTL_GPIO_OUT_SET, PIN_DAC_CLK )
#define SetDacClkLow(x)  	ioctl( x, IOCTL_GPIO_OUT_CLR, PIN_DAC_CLK )

#define SetDacDinHigh(x)  	ioctl( x, IOCTL_GPIO_OUT_SET, PIN_DAC_DIN )
#define SetDacDinLow(x)  	ioctl( x, IOCTL_GPIO_OUT_CLR, PIN_DAC_DIN )

#define	SetDACPort()										\
	do{ 													\
		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_DAC_CS );		\
		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_DAC_CLK );		\
		ioctl( fd, IOCTL_GPIO_DIR_OUT, PIN_DAC_DIN );		\
		SetDacCsHigh(fd);									\
		SetDacClkLow(fd); 									\
		SetDacDinHigh(fd); 									\
	}while(0)
	
#define  FPGAHandle	fdFPGA

/*-----------------------------------
|  FPGA  ADDRESS  Access Define     |
------------------------------------*/
extern unsigned short usFPGABuf;



/*Read Byte*/
//#define	GetFPGAValue(Addr)	0 //( (*Addr) & 0x00FF )

//#################################################################################################################################
#define GetFpgaValue(Addr)					(ioctl( FPGAHandle, IOCTL_FPGA_READ, Addr )&0xFF)
#define SetFpgaValue(Addr,v)				ioctl( FPGAHandle, IOCTL_FPGA_WRITE, (  ( ((Addr)<<16) & 0xFFFF0000 )  +  (v)  ) )

#define GetFpgaValue2nd(Addr)					(ioctl( FPGAHandle, IOCTL_FPGA_READ, Addr )&0xFF)
#define SetFpgaValue2nd(Addr,v)				ioctl( FPGAHandle, IOCTL_FPGA_WRITE, (  ( ((Addr)<<16) & 0xFFFF0000 )  +  (v)  ) )

#define SetFpgaAddr32(Addr)					ioctl( FPGAHandle, IOCTL_FPGA_SET_ADDR_32BIT, Addr )
#define GetFpgaValue32(Addr)				ioctl( FPGAHandle, IOCTL_FPGA_READ, Addr )
#define SetFpgaValue32(Addr,v)				do{ SetFpgaAddr32(Addr); ioctl( FPGAHandle, IOCTL_FPGA_WRITE_32BIT, v ); }while(0)



#define GetFpgaValueInt(Addr)				(ioctl( FPGAHandle, IOCTL_FPGA_READ_INT, Addr )&0xFF)
#define SetFpgaValueInt(Addr,v)				do{ SetFpgaAddrInt(Addr); ioctl( FPGAHandle, IOCTL_FPGA_WRITE_INT, v ); }while(0)

#define GetFpgaValueFD(FPGAHandle,Addr)		(ioctl( FPGAHandle, IOCTL_FPGA_READ, Addr )&0xFF)
#define SetFpgaValueFD(FPGAHandle,Addr,v)	ioctl( FPGAHandle, IOCTL_FPGA_WRITE, (  ( ((Addr)<<8) & 0xFF00 )  +  (v)  ) )

//#################################################################################################################################


//Bit Write
#define	SetBitHigh(Addr,x)		SetFpgaValue((Addr),GetFpgaValue(Addr)|(x) )
#define	SetBitLow(Addr,x)		SetFpgaValue((Addr),GetFpgaValue(Addr)&~(x) )

//Bit Query
#define	IsBitHigh(Addr,x)	 	( (GetFpgaValue(Addr) &  (x) )== (x) )
#define	IsBitLow(Addr,x)	  	( (~GetFpgaValue(Addr) &  (x) )== (x) )
//#################################################################################################################################



#define GetCounterx(x)			( ( ((GetFpgaValue(x+2)&(~0x1))>>1)*100000)   + ( (GetFpgaValue(x+2)&0x1)<<16)  + (GetFpgaValue(x+1)<<8) + (GetFpgaValue(x))   )
									
#define GetCounterAllx(x)		( (GetFpgaValue(x+3)*10000000)+ \
									( ((GetFpgaValue(x+2)&(~0x1))>>1)*100000) + ( (GetFpgaValue(x+2)&0x1)<<16)  + (GetFpgaValue(x+1)<<8) + (GetFpgaValue(x))   )

#define GetCounterAll()			GetCounterAllx(0)
#define GetCounterAll2nd()		GetCounterAllx(4)

#define ReadMainCounter()		GetCounterx(0)
#define ReadMainCounterAll()	GetCounterAllx(0)

#define Read10E6Counter()		ReadMainCounter()

#define GetCounterTraceAll()	GetCounterAllx(28)
#define GetCounterTrace()		GetCounterx(28)

#define ReadTraceCounterFPGA()  GetCounterTraceAll()	 // need to redefined
#define ReadTraceCounter()  	GetCounterTrace()	

/////////////////// 			 ///////////////////////////////
///////////////////   FPGA Address(0:5), Data(0:7) Bit Read     ///////////////////////////////
///////////////////             ////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////

#define FPGA_Addr_			4
#define FPGA_Data_			0

#define M_None1			wbD0
#define M_None2			wbD1

#define M_A2				wbD2
#define M_A3				wbD3
#define M_A0				wbD4
#define M_A1				wbD5
#define M_A4				wbD6
#define M_A5				wbD7

#define M_D0				wbD0
#define M_D1				wbD1
#define M_D2				wbD2
#define M_D3				wbD3
#define M_D4				wbD4
#define M_D5				wbD5
#define M_D6				wbD6
#define M_D7				wbD7

#define	IsBitHigh2nd(Addr,x)	 	( (GetFpgaValue2nd(Addr) &  (x) )== (x) )

#define	QueryFPGAAddr0()		IsBitHigh2nd (FPGA_Addr_, M_None1)
#define	QueryFPGAAddr1()		IsBitHigh2nd (FPGA_Addr_, M_None2)
#define	QueryFPGAAddr2()		IsBitHigh2nd (FPGA_Addr_, M_A2)
#define	QueryFPGAAddr3()		IsBitHigh2nd (FPGA_Addr_, M_A3)
#define	QueryFPGAAddr4()		IsBitHigh2nd (FPGA_Addr_, M_A0)
#define	QueryFPGAAddr5()		IsBitHigh2nd (FPGA_Addr_, M_A1)
#define	QueryFPGAAddr6()		IsBitHigh2nd (FPGA_Addr_, M_A4)
#define	QueryFPGAAddr7()		IsBitHigh2nd (FPGA_Addr_, M_A5)

#define	QueryFPGAData0()		IsBitHigh2nd (FPGA_Data_, M_D0)
#define	QueryFPGAData1()		IsBitHigh2nd (FPGA_Data_, M_D1)
#define	QueryFPGAData2()		IsBitHigh2nd (FPGA_Data_, M_D2)
#define	QueryFPGAData3()		IsBitHigh2nd (FPGA_Data_, M_D3)
#define	QueryFPGAData4()		IsBitHigh2nd (FPGA_Data_, M_D4)
#define	QueryFPGAData5()		IsBitHigh2nd (FPGA_Data_, M_D5)
#define	QueryFPGAData6()		IsBitHigh2nd (FPGA_Data_, M_D6)
#define	QueryFPGAData7()		IsBitHigh2nd (FPGA_Data_, M_D7)

#define 	QueryFPGAAddr()		(QueryFPGAAddr0()<<0)+(QueryFPGAAddr1()<<1)+(QueryFPGAAddr2()<<2)+(QueryFPGAAddr3()<<3)+\
										(QueryFPGAAddr4()<<4)+(QueryFPGAAddr5()<<5)+(QueryFPGAAddr6()<<6)+(QueryFPGAAddr7()<<7)

#define 	QueryFPGAData()		(QueryFPGAData0()<<0)+(QueryFPGAData1()<<1)+(QueryFPGAData2()<<2)+(QueryFPGAData3()<<3)+\
										(QueryFPGAData4()<<4)+(QueryFPGAData5()<<5)+(QueryFPGAData6()<<6)+(QueryFPGAData7()<<7)

#define 	Print_FPGAAddr()		Print_Binary(QueryFPGAAddr())

#define 	Print_FPGAData()		Print_Binary(QueryFPGAData())


/************************************** FPGA Config Flag **************************************/
#define ReadFPGAConfigValue()		0 //GetFPGAValue(FPGAConfigFlagAddr)
/************************************** FPGA Config Flag **************************************/


/////////////////// 			 ///////////////////////////////
///////////////////    Dual      ///////////////////////////////
///////////////////             ////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////

#define DualCmdAddr			24

#define M_BLOCK				wbD0
#define M_SELF_BLOCK		wbD1
#define M_CLR_FAIL			wbD2
#define M_CLR_U_FAIL		wbD3

#define M_Status_LGE		wbD4
#define M_ClrEventLatch		wbD5
#define M_Fail_LGE			wbD6
#define M_Ready_LGE			wbD7

//#define M_BLOCK			wbD0
#define	QueryForceBlock()		IsBitHigh ( DualCmdAddr, M_BLOCK )

//#define ClearMyFail();			do{ SetBitHigh ( DualCmdAddr, M_CLR_FAIL ); SetBitLow ( DualCmdAddr, M_CLR_FAIL ); }while(0);
#define ClearYourFail();		do{ SetBitHigh ( DualCmdAddr, M_CLR_U_FAIL ); SetBitLow ( DualCmdAddr, M_CLR_U_FAIL ); }while(0);

//#define M_SELF_BLOCK		wbD1
#define SetMeToSelfBlock()		SetBitHigh( DualCmdAddr, M_SELF_BLOCK )
#define DisableSelfBlock()		SetBitLow( DualCmdAddr, M_SELF_BLOCK )
#define	QuerySelfBlock()		IsBitHigh( DualCmdAddr, M_SELF_BLOCK )


//#define SetStatusLGE();		SetBitHigh( DualCmdAddr, M_Status_LGE );
//#define ResetStatusLGE();		SetBitLow( DualCmdAddr, M_Status_LGE );

//#define SetFailLGE();			SetBitHigh( DualCmdAddr, M_Fail_LGE );
//#define ResetFailLGE();		SetBitLow( DualCmdAddr, M_Fail_LGE );

#define SetReadyLGE();			SetBitHigh( DualCmdAddr, M_Ready_LGE );
#define ResetReadyLGE();		SetBitLow( DualCmdAddr, M_Ready_LGE );


#define SetMeActive();			SetBitHigh( DualCmdAddr, M_Status_LGE );
#define SetMeNotActive();		SetBitLow( DualCmdAddr, M_Status_LGE );

#define SetMeFail();			SetBitHigh( DualCmdAddr, M_Fail_LGE );
#define ClearMyFail();			SetBitLow( DualCmdAddr, M_Fail_LGE );

#define AreYouSwitchReady()		IsBitLow( DualReadAddr, M_U_Ready_LGE ) 
#define SetMeSwitchReady();		SetBitHigh( DualCmdAddr, M_Ready_LGE );
#define SetMeSwitchNotReady();	SetBitLow( DualCmdAddr, M_Ready_LGE );

//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////

#define DualSetBit	25

#define M_ALLOW_DUAL_EVENT			wbD0
#define M_EN_EVENT_ON_MY_FAIL		wbD1
#define M_EN_EVENT_ON_YOUR_FAIL		wbD2
#define M_EVENT_CLK					wbD3
#define M_EN_SIG					wbD4 


///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////

#define DualReadAddr 26


#define M_DELETING 			wbD0
#define M_MODULE_ID			wbD1
#define M_U_Fail_LGE		wbD2 
#define M_U_SELF_BLOCK  	wbD3 
#define M_U_NOT_EXIST		wbD4
#define M_U_STATUS_LGE     	wbD5
#define M_U_Ready_LGE     	wbD6
#define M_SIG_ONOFF_RESULT	wbD7
///////////////////////////////////////////////////////////////

#define AreYouAlive()			IsBitLow( DualReadAddr, M_U_NOT_EXIST )


#define AreYouReadyLGE()		IsBitLow( DualReadAddr, M_U_Ready_LGE ) 
#define AreYouFailLGE()			IsBitLow( DualReadAddr, M_U_Fail_LGE )

#define AreYouActiveLGE()		IsBitLow( DualReadAddr, M_U_STATUS_LGE )
#define	AreYouActive()			IsBitLow( DualReadAddr, M_U_STATUS_LGE )

#define AmIDeleting()		IsBitHigh( DualReadAddr, M_DELETING )
#define AreYouExist()		IsBitLow( DualReadAddr, M_U_NOT_EXIST )
#define IsSigOn()			IsBitLow( DualReadAddr , M_SIG_ONOFF_RESULT )

#define IsAModule() 		IsBitLow( DualReadAddr ,M_MODULE_ID )	//Lower:B   Upper:A   
//#define IsAModule() 		IsBitHigh( DualReadAddr ,M_MODULE_ID )	//Lower:A   Upper:B

///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
//#########################################################################################################
//#########################################################################################################
//#########################################################################################################


//#define SetMeFail();				SetFailLGE();
//#define AreYouSwitchReady()		AreYouReadyLGE()
//#define SetMeSwitchReady();		SetReadyLGE();
//#define SetMeSwitchNotReady();	ResetReadyLGE();



#define	QueryYourForceBlock()	0      
#define	QueryYourSelfBlock()	0      




//#define	IsRbModel() 0
#define	IsRbModel() 1	//sewon rb
//#########################################################################################################
//#########################################################################################################
//#########################################################################################################

////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////

#define SetSigOnOffHigh(x);		SetBitHigh(DualSetBit,x);
#define SetSigOnOffLow(x);		SetBitLow (DualSetBit,x);


/**************************************VV Counter Control **************************************/
#define CounterControlAddr 	10
#define IsCounterControlHigh(x)		IsBitHigh(CounterControlAddr,x)
#define IsCounterControlLow(x)		IsBitLow(CounterControlAddr,x) 

#define SetCounterControlHigh(x);	SetBitHigh(CounterControlAddr,x);
#define SetCounterControlLow(x);	SetBitLow(CounterControlAddr,x);

#define M_CLR_MAIN_COUNTER					wbD4
#define M_CLR_TRACE_COUNTER					wbD1

#define M_MAIN_COUNTER_CLR_SRC				wbD2

#define M_VALUE_DUAL_TX						wbD5
#define M_SEL_DUAL_TX						wbD6
#define M_BLOCK_DUAL_EVNT					wbD3
#define M_RESET_PHY							wbD7


//#define M_ADJUST_1PPS0					wbD4
//#define M_ADJUST_1PPS1					wbD5

//#define M_SELECT_1PPS_CLR_SRC				wbD6
//#define M_SELECT_1PPS_IRQ_SRC				wbD7


#define Clear1PPSwithGPS_Ext1pps();		SetCounterControlLow( M_MAIN_COUNTER_CLR_SRC); SetCounterControlLow(M_CLR_MAIN_COUNTER); SetCounterControlHigh(M_CLR_MAIN_COUNTER);
//#define Clear1PPSwithGPS();		SetCounterControlLow( M_MAIN_COUNTER_CLR_SRC); SetCounterControlLow(M_CLR_MAIN_COUNTER); SetCounterControlHigh(M_CLR_MAIN_COUNTER);
#define Clear1PPSWithU1PPS();	SetCounterControlHigh(M_MAIN_COUNTER_CLR_SRC); SetCounterControlLow(M_CLR_MAIN_COUNTER); SetCounterControlHigh(M_CLR_MAIN_COUNTER);

#define BlockDualTxEvnt();		SetCounterControlHigh(M_BLOCK_DUAL_EVNT);
#define ReleaseDualTxEvnt();	SetCounterControlLow( M_BLOCK_DUAL_EVNT);

#define SetDualTxModeToTest();		do{	BlockDualTxEvnt(); 	 SetCounterControlHigh(M_SEL_DUAL_TX); 					}while(0);
#define SetDualTxModeToOperation();	do{	ClearYourFail(); ReleaseDualTxEvnt(); SetCounterControlLow(M_SEL_DUAL_TX);	}while(0);
//#define SetDualTxModeToTest();		SetCounterControlHigh(M_SEL_DUAL_TX);
//#define SetDualTxModeToOperation();	SetCounterControlLow(M_SEL_DUAL_TX);

#define SetDualTxValueToHigh();		SetCounterControlHigh(M_VALUE_DUAL_TX);
#define SetDualTxValueToLow();		SetCounterControlLow(M_VALUE_DUAL_TX);

#define AssertResetToPHY();			do{	SetCounterControlHigh(M_RESET_PHY); SetCounterControlLow(M_RESET_PHY); }while(0);
#define AssertResetToPHYHigh();		do{	SetCounterControlHigh(M_RESET_PHY); }while(0);

#define GetDualTxValueReceived()			GetFpgaValue(11)



#define GetDualTP()					GetFpgaValue(27)

#define AssertResetToRCV();			do{	SetBitHigh(12,wbD6); SetBitLow(12,wbD6); }while(0);
#define Select1PPS_TP(x);			do{	SetBitLow(12,wbD0|wbD1|wbD2|wbD3); SetBitHigh(12,x); }while(0);


//#########################################################################################################
#define WdtAddr				36
#define WdtClear			wbD0	
#define OpenClear			wbD2
#define SelTODFPGA			wbD3
#define RstTODFPGA			wbD4
#define Sel10MHzForDual		wbD5

#define ClearFPGAWdt();		//do{ SetBitHigh(WdtAddr, WdtClear); SetBitLow(WdtAddr, WdtClear); } while(0);
									//Sewon 120509
#define ClearFPGAOpenDetect();		//do{ SetBitHigh(WdtAddr, OpenClear); SetBitLow(WdtAddr, OpenClear); } while(0);
												//Sewon 120509
#define SelTodFPGA();	//	SetBitHigh(WdtAddr, SelTODFPGA);
#define SelTodCPU();		//SetBitLow(WdtAddr, SelTODFPGA);

#define ResetTODFpga();		//do{ SetBitHigh(WdtAddr, RstTODFPGA); SetBitLow(WdtAddr, RstTODFPGA); } while(0);

#define Sel_10MHz_Dual();		//SetBitHigh(WdtAddr, Sel10MHzForDual);
#define Sel_IntOsc_Dual();		//SetBitLow(WdtAddr, Sel10MHzForDual);

#define WriteTODDataFPGA(x);	SetFpgaValue(45,(x));

#define FANALMaddr			37
#define FAN1				wbD0 //the front FAN	
#define FAN2				wbD1 //the backside FAN	
//#define QueryFANALM1()		IsBitLow(FANALMaddr, FAN1)
//#define QueryFANALM2()		IsBitLow(FANALMaddr, FAN2)
#define QueryFANALM1()		IsBitHigh(FANALMaddr, FAN1)
#define QueryFANALM2()		IsBitHigh(FANALMaddr, FAN2)
#define QueryFANOPEN()		IsBitHigh(FANALMaddr, wbD2)
//#define QueryFANError()		(QueryFANALM1() || QueryFANALM2() || QueryFANOPEN() )
#define QueryFANError()		(QueryFANALM1() || QueryFANALM2() )
//#########################################################################################################
//#define SelectExt1PPSRef();		do{ UnconditionalSigOff1(); SetBitHigh(36, wbD1); } while(0);
//#define DeSelectExt1PPSRef();		do{ UnconditionalSigOn1(); SetBitLow(36, wbD1); } while(0);
#define SelectExt1PPSRef()		//SetBitHigh(36, wbD1)
#define DeSelectExt1PPSRef()	//SetBitLow(36, wbD1)
//#########################################################################################################

/*
#define SetFuncFail()		SetBitHigh(44, wbD0)
#define ResetFuncFail()		SetBitLow( 44, wbD0)

#define SetFanFail()		SetBitHigh(44, wbD1)
#define ResetFanFail()		SetBitLow( 44, wbD1)
*/

#define SetFuncFail()
#define ResetFuncFail()

#define SetFanFail()
#define ResetFanFail()

#define SetRCUFuncFail()		SetBitLow(44, wbD0)
#define ResetRCUFuncFail()		SetBitHigh( 44, wbD0)

#define SetRCUClkFail()			SetBitLow(44, wbD1)
#define ResetRCUClkFail()		SetBitHigh( 44, wbD1)


#define ClearEvntLatch()	do{ SetBitHigh( 24,M_ClrEventLatch); SetBitLow( 24,M_ClrEventLatch); }while(0)
#define GetDualEvntLatch()	( (int)(GetFpgaValue(21)) + ( ((int)GetFpgaValue(22))<<8) )

#define GetEvents() 					\
	( (int)(GetFpgaValue(21)) + 		\
	( ((int)GetFpgaValue(22))<<8) + 	\
	( ((int)GetFpgaValue(24))<<16) +	\
	( ((int)GetFpgaValue(26))<<24))
	
//////////////////////////
///////////////////////////
///////  Dummy Definition to in future use or to prevent compile error.

extern int TRACE_OFFSET,TRACE_DIFFERENCE;

#define ReadSynthCounter() 0
#define SetDetailOutputTraceCounter();
#define SetDetailOutputMainCounter();
#define IsX72Lock() 0
#define IsSRO100Lock() 	rb.sro100.quality
#define ClearPP2SWith1PPS();

#define ResetPwrFail();
#define SetPwrFail();

#define Select8KCounter1();
#define Select8KCounter2();
#define ResetClear8KCounter();
#define SetClear8KCounter();
#define Read8KCounter()     0
#define ReadLMUCounter()    0

#define Select1PPSEb();
#define Select1PPS8K1();

#define DisableSccFPGATxRxInt();
#define SetResetSignal();
#define SystemReset();

#define SetDACPWM(x);

#define SetPLLConfigPin();
#define SetPLL_LE_High();
#define SetPLL_LE_Low();
#define SetPLL_DATA_High();
#define SetPLL_DATA_Low();
#define SetPLL_CLK_High();
#define SetPLL_CLK_Low();
//kang #define SetMeSwitchNotReady();
//kang #define SetMeNotActive();
#define Select1PPSOutwithEB();
#define DeSelect1PPSOutwithEB();
#define SelectCenterForDetail_50ns();
#define SelectU1PPSForDetail_50ns();
#define EnableClockFailLatch();
//kang #define SetMeSwitchReady();



extern void fpga_init(int fd);
extern void ChangeDACValue(int fd, int volt);
extern void Print_Binary(unsigned char input);	//sewon

#endif



